1. Field of the Invention
The present invention relates to a bump and a method of manufacturing the same and, more particularly, to a bump selectively formed on the surface of an electrode and capable of being well-connected to an external wiring layer, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, with the advances made in the miniaturization of electronic devices, integration densities of IC's and LSI's have been greatly increased. In mounting of semiconductor elements onto a substrate, the distance (pitch) between electrode is reduced and the number of I/O terminals is increased. Incidentally in card type calculators and IC cards, a demand has arisen for developing low-profile products which require short pitches.
By the way, since wireless bonding such as a TAB and a flip chip can advantageously realize collective bonding of electrodes and high-precision alignment between electrodes, low-profile and automatic mounting of semiconductor elements with high reliability can be expected. Therefore, the wireless bonding becomes a mainstream of mounting techniques of LSI chips from now on. In performing wireless bonding, metal projections known simply as bumps are generally formed on aluminum electrodes of LSI chips. FIGS. 1A to 1D illustrate the steps involved in forming these bumps according to the conventional method.
First, as is shown in FIG. 1, passivation film 3, composed of SiO.sub.2 or Si.sub.3 N.sub.4, is formed on the entire surface of semiconductor wafer 1 on which is already formed Al electrode 2. Next, passivation film 3 is selectively etched to expose most of Al electrode 2. Thereafter, as is shown in FIG. 1B, underlying metal film 4 is formed on the entire surface of wafer 1, including passivation film 3, by deposition or by sputtering, and resist pattern 5 is formed thereon, by use of a photo engraving process (PEP), except for that portion of metal film 4 which corresponds to Al electrode 2. Next, as is shown in FIG. 1C, metal projection 6 is selectively formed, by electroplating, on a portion including part of exposed underlying metal film 4, with film 4 serving as a cathode in this process. After resist pattern 5 is removed, exposed underlying metal film 4 is removed using metal projection 6 as a mask to form the bump (FIG. 1D).
The above conventional bump forming method, has the following drawbacks, however. To begin with the conventional method entails a large number of processing steps, such as the formation of the underlying metal film, formation of the resist pattern by a PEP, removal of the resist pattern after electroplating, and etching of the underlying metal film, resulting in a high manufacturing cost. Furthermore, in these steps, many substances involved in etching, PEP etc. are likely to contaminate the LSI chips. In addition, since the above method for forming the bump is practiced on a wafer, bumps cannot be formed on LSI chips obtained by dicing a wafer. For this reason, if a wafer has LSI chips having defective semiconductor elements, the inefficiency to form bumps on the LSI chips including the defective elements cannot be avoided.
For these reasons, an attempt has been made to form bumps on only the diced LSI chips having no defective semiconductor elements by electroless palladium-activated nickel plating. In the conventional electroless plating, zinc substitution is applied as a pretreatment. However, since a substitution solution in the zinc substitution is a strong alkali, the LSI chips may be adversely affected, e.g., a silicon substrate and the Al electrode are corroded. In this case, since the palladium is precipitated on the allover surfaces of the chips including passivation film, and activates the surfaces, nickel films are precipitated on not only the electrodes but also the passivation films during the following electroless nickel plating process. As a result, an electrical short circuit may occur between the bumps through the nickel films precipitated on the passivation films. In particular, when bump intervals are reduced with high integration densities of the LSI chips, short-circuiting frequently occurs between these bumps, thereby causing the reduction in yield.